Security Trends for FPGAS by Benoit Badrignans Jean Luc Luc Danger Viktor Fischer Guy Gogniat & Lionel Torres

Author:Benoit Badrignans, Jean Luc Luc Danger, Viktor Fischer, Guy Gogniat & Lionel Torres
Language: eng
Format: epub
Publisher: Springer Netherlands, Dordrecht

4.4.6 Comparison of DPL Families

Table 4.3 compares robustness, speed and complexity of a few DPLs. In fact, it is difficult to evaluate robustness fairly, as the DPL countermeasure depends on the target technology and the quality of the P/R stages. However most non-synchronized DPL, such as WDDL and MDPL have been attacked without any particular P/R effort [42, 44, 57]. The analysis of DPL robustness is still an ongoing research project. Some ideas come from the information theory with mutual information analysis [15] and the stochastic approach [47]. In Table 4.3, robustness against SCA is indicated by the logic capacity to be insensitive to early evaluation and technological bias. The fault column indicates if the logic able to cope with symmetric fault (faults being ‘1’ or ‘0’), which is preferable, rather than asymmetric. Fault detection can be combinatorial or sequential. If it is sequential the cost is higher. Table 4.3Comparison of robustness, complexity and speed of a few DPLs

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